Intepro Systems

ISO 16750-2

ISO 16750-2 Automotive Electrical Loads Testing

Revision 2023 (fifth edition), replaces ISO 16750-2:2012

Programmable DC source covering 0–36 V steady state with millisecond profile sequencing — cranking waveforms with 2 Hz ripple and 1 ms transient edges — plus superimposed AC ripple injection from 10 Hz to 200 kHz at up to 15 A peak-to-peak, slow ramps down to 0.5 V/min, and polarity reversal to −26 V. Micro interruptions need a series switch that opens in ≤ 10 µs to ≥ 10 MΩ, and load dump needs a pulse delivered from a defined 0.5–8 Ω source resistance at up to 202 V peak — a specified source-impedance pulse, not just a voltage setpoint.

This standard turns on

  • supply-voltage code system (A–H)
  • cranking and starting profiles
  • load dump
  • superimposed ripple to 200 kHz
  • micro interruptions

And says nothing about

  • EMC and radiated immunity — 4.13 points out to the EMC standards
  • high-voltage traction buses (LV 123 territory)
  • 400 Hz aviation power
  • reliability-duration testing
  • grid ride-through

Cited limits

Every value carries the clause, table or figure it comes from.

ParameterValueClause
Supply-voltage codes, 12 V systemsCode A 6–16 V; B 8–16 V; C 9–16 V; D 10.5–16 V; Z as agreedTable 3
Supply-voltage codes, 24 V systemsCode E 10–32 V; F 16–32 V; G 22–32 V; H 18–32 V; Z as agreedTable 4
Long-term overvoltage (alternator regulator failure)18 V (12 V systems) / 36 V (24 V systems) for 60 min at Tmax − 20 K§4.3.1.1
Jump start (12 V systems only)26 V for 60 ± 6 s, rise/fall ≤ 10 ms, from USmin 10.8 VTable 5 / Figure 2
Transient overvoltage18 V (12 V) / 36 V (24 V) for 400 ms, rise/fall 1 ms (12 V) or 2 ms (24 V), 5 pulses at 1 s restTable 6 / Figure 3
Superimposed alternating voltage10 Hz–200 kHz sweep, 2 % logarithmic steps; severity 1 Upp 6 V (12 V) / 10 V (24 V); severity 4 Upp 1 V at 30–200 kHz; ripple current limit 15 A (f1) / 10 A (f2)Table 7 / Table 8
Slow decrease and increase of supply voltageUA → 0 V → UA at (0.5 ± 0.1) V/min, linear or steps ≤ 25 mV§4.5.2 / Figure 6
Micro interruption in supply voltagetmicro 10 µs–2 s stepped from 10 µs; switch reaction ≤ 10 µs; open-switch resistance ≥ 10 MΩTable 9 / §4.6.1.2
Reset behaviour at voltage dropstaircase in 5 % steps of USmin down to 0 V, ≥ 5 s per drop, functional check at each return to USmin§4.6.2.2 / Figure 12
Starting profile (24 V, severest level)drop to US1 6 V for 50 ms, then cranking plateau US 10 V with 2 Hz ripple; profile applied 10 times, ≥ 2 s recoveryTable 12 / Figure 13
Load dump, Test A (no centralized suppression)US 79–101 V (12 V) / 151–202 V (24 V); Ri 0.5–4 Ω / 1–8 Ω; td 40–400 ms / 100–350 ms; 10 pulses at 1 min intervalsTable 13 / Figure 14
Load dump, Test B (centralized suppression)clamped US* 27/30/32/35 V at severity 1–4 (12 V); 24 V as specified, typical 58 V; 5 pulses at 1 min intervalsTable 14 / Figure 15
Reversed voltage−14 V (12 V) / −26 V (24 V) for 60 s (test case 2); −4 V for 60 s (test case 1, 12 V only)Table 15 / Table 16

Where these figures came from

Each record below backs a specific part of this page. Where a table sits behind a paywall we say so above rather than reproducing it.

Further reading

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