JEDEC JESD22 / JESD47
JEDEC Power Semiconductor Reliability Testing
Regulated high-voltage DC bias across 77+ devices per lot for 1000 h with per-device leakage monitoring and fail-isolation — one shorted die must not collapse bias on the rest — plus interim parametric reads at 168/500/1000 h.
This standard turns on
- hours at temperature
- bias stability over 1000 h
- per-device leakage monitoring
- channel density
And says nothing about
- AC waveform synthesis
- 400 Hz
- grid ride-through
- harmonics
Cited limits
Every value carries the clause, table or figure it comes from.
| Parameter | Value | Clause |
|---|---|---|
| HTOL | Tj ≥125 °C, Vcc ≥ Vcc,max, 3 lots × 77 units, 1000 h, 0 fails | JESD47 |
| HTOL method | static or dynamic bias at max operating voltage, Tj 125–150 °C | JESD22-A108 |
| HTRB | Tj = Tj,max (150–175 °C for SiC), V_DS = 80% of rated blocking voltage, 1000 h | MIL-STD-750-1 M1038/M1039 + JEDEC practice |
| H3TRB / THB | 85 °C / 85% RH, reverse bias 80% of rated V capped at 100 V, 1000 h | JESD22-A101 / AEC-Q101 |
Equipment for this standard
Further reading
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