Power Semiconductors (SiC / IGBT)
Testing discrete SiC and IGBT devices, power modules on high-voltage DC bias, hundreds to 1700 V class. What you are proving is that the device survives 1000 hours of stress without parametric drift.
- Device under test
- discrete SiC and IGBT devices, power modules
- Bus
- high-voltage DC bias, hundreds to 1700 V class
- Who buys this
- device makers and automotive qualification teams
Nothing about this is fast. It is bias accuracy held for a thousand hours across a lot of devices, with the discipline that one failure cannot disturb the rest.
Where programmes get caught out
One shorted die must not take the lot
Fail-isolation per device is the requirement that separates a reliability rig from a bench supply with a fan-out.
Bias accuracy is the acceleration variable
Error in the applied bias is error in the inferred lifetime. Nothing else in the rig matters as much.
Interim reads shape the data, not just the pass
168, 500 and 1000-hour checkpoints determine whether you can see drift coming or only its aftermath.
Where the standards have moved
Revision status changes what your report has to cite. Every note below carries the record it came from, retrieved on the date shown.
JC-70.2 has published named guidelines — cite the number, not "JEDEC"
The silicon-carbide subcommittee's published set now includes JEP183A on measuring threshold voltage, JEP184 on bias temperature instability, JEP187 on representing switching losses in datasheets, JEP190 on dv/dt robustness, JEP194 on gate-oxide reliability and robustness, and JEP204, a catalogue of stress procedures for SiC power-conversion devices. JEP183 was the subcommittee's first publication, announced on 2 February 2021 and free to download. A qualification plan that cites "JEDEC" without a JEP number has not said what it is doing.
Source: JEP183A, JEP184, JEP187, JEP190, JEP194 and JEP204 document records — JEDEC Solid State Technology Association. Retrieved 2026-08-24.
There is still no SiC equivalent of AEC-Q101 or JESD47
A Wolfspeed review of the standards landscape notes that alignment between JEDEC, IEC and ECPE has not been reached on even some major aspects of the stress procedures, let alone on a single qualification guideline. IEC has published 63275-1 and 63275-2, both Edition 1.0 dated 2022, on bias temperature instability and bipolar degradation, and JC-70.2 continues work on bipolar stability, gate-oxide reliability and HTRB. The practical consequence for the test floor is that a qualification plan is assembled from guidelines rather than run from one named sequence, so the ATE has to hold arbitrary bias and temperature combinations for the full stress duration instead of executing a fixed script.
Source: Reliability and Standardization for SiC Power Devices — Donald A. Gajewski and colleagues, Materials Science Forum vol. 1092. Retrieved 2026-08-24.
Testing to a standard
The clause-by-clause limits, and what each standard deliberately says nothing about.
Equipment for this work
- SemTest Power Semiconductor Reliability ATEPower-semiconductor reliability ATE for SiC and IGBT qualification — high-voltage bias held across a lot of devices for the full stress duration, with per-device leakage monitoring.
- Vega Series Customizable Power Racks15 kW – 480 kWCustomisable high-power racks built from 15 kW 3U regenerative loads and DC supplies — mixed and matched to the test requirement rather than bought as a fixed configuration.
Specifying a bench for semiconductor?
Send the clause you have to satisfy rather than a shopping list. An engineer will tell you what the rig has to do — including the parts of the programme this equipment does not cover.
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