Intepro Systems

H3TRB Testing: What Biased Humidity Asks of the Rig That Dry Heat Does Not

Power semiconductors · 4 min read · 13 cited facts

Dry high-temperature reverse bias asks the rig for voltage — most of the device's rated blocking capability, held hot for the full stress duration. The humid sibling asks for almost none of it. H3TRB, also written THB, biases the device at 80% of rated voltage but capped at 100 V, inside a chamber held at 85 °C and 85% relative humidity, for 1000 h, under JESD22-A101 and AEC-Q101.

That low bias is not a relaxation. The mechanism being hunted needs the package wet, and a die dissipating meaningful power dries its own encapsulant from the inside — a device that self-heats is quietly running a milder test than the one on the report. So where the dry test demands field stress, the humid one demands restraint: a small voltage held perfectly, through a chamber wall, for the full 1000 h.

What the condition is hunting

ParameterValueClause
H3TRB / THB85 °C / 85% RH, reverse bias 80% of rated V capped at 100 V, 1000 hJESD22-A101 / AEC-Q101
The biased-humidity stress condition

Reverse bias in a humid chamber is not there to stress the junction; it is there to drive ions. Moisture that reaches the die surface becomes an electrolyte, and the bias turns package contamination into electrochemical transport — corrosion of metallisation, dendritic growth, migration across passivation. The failures are chemical, which is why they arrive as gradual leakage drift at least as often as abrupt shorts, and why the measurement side of the rig matters more than the power side.

The chamber owns the schedule

The condition has to survive its own fixturing. Bias has to enter the chamber and per-device leakage measurement has to come back out — through feedthroughs, across 1000 h at 85 °C and 85% RH, without the wiring itself corroding, condensing, or leaking current at the level the measurement is trying to resolve. A rig that holds voltage beautifully on a bench and cannot make that round trip through a chamber wall is not an H3TRB rig.

Per-device monitoring at low bias

The cap changes what failure looks like at the instrument. At 100 V the leakage budget per device is small and drift within it is the data, so monitoring has to be per device — and so does isolation. One part going resistive must not pull the shared bias down for the rest of the lot, or the 1000 h clock restarts for everyone.

This is the part of the architecture SemTest was built around: per-DUT current monitoring that cuts the supply on limit while every other device keeps testing, and electrical stress removed within 30 ms of a device starting to fail. For a chemical failure mode, preserving the part for failure-mode analysis is much of the reason the test was run at all.

One more thing worth planning around: there is still no SiC equivalent of a single named qualification sequence. A published review of the SiC standards landscape notes that alignment between JEDEC, IEC and ECPE has not been reached on major aspects of the stress procedures; IEC has issued IEC 63275-1 and 63275-2, both Edition 1.0 dated 2022, on bias temperature instability and bipolar degradation, and JC-70.2 continues work. The practical consequence for humid-bias capacity is that the rig gets specified for the plan you assemble, not for a script you buy — holding arbitrary bias and condition combinations for the full duration is a requirement, not a convenience.

Specifying humid-bias capacity?

Tell us the device class, the lot size, and whether the plan is JESD22-A101, AEC-Q101 or a higher-voltage variant. We will be direct about what the chamber integration costs and where the measurement floor sits.

Talk to an engineer

Related

More on power semiconductors