JEDEC SiC Qualification by Document Number: The JC-70.2 Set

Power semiconductors · 3 min read · 25 cited facts

A qualification plan that cites "JEDEC" without a JEP number has not said what it is doing. For silicon that vagueness is survivable, because JESD47 exists and everyone knows the sequence it implies. For silicon carbide there is no such sequence to imply — there is a set of named guidelines, and a plan has to say which of them it is running.

The published JC-70.2 set

JEDEC's silicon-carbide subcommittee, JC-70.2, has a published set a plan can cite by number:

• JEP183A — measuring threshold voltage. JEP183 was the subcommittee's first publication, announced on 2 February 2021 and free to download.
• JEP184 — bias temperature instability.
• JEP187 — representing switching losses in datasheets.
• JEP190 — dv/dt robustness.
• JEP194 — gate-oxide reliability and robustness.
• JEP204 — a catalogue of stress procedures for SiC power-conversion devices.

Those document numbers are verified against the JEDEC catalogue. Their internal clause numbering is deliberately not reproduced here — the documents themselves are the reference for stress conditions, and a plan should quote them directly.

What still does not exist

There is no SiC equivalent of AEC-Q101 or JESD47. Alignment between JEDEC, IEC and ECPE has not been reached on even some major aspects of the stress procedures, let alone on a single qualification guideline. IEC has published IEC 63275-1 and IEC 63275-2, both Edition 1.0 dated 2022, on bias temperature instability and bipolar degradation, and JC-70.2 continues work on bipolar stability, gate-oxide reliability and HTRB.

The numbers a plan still borrows from silicon practice

The reverse-bias hold follows the same pattern: HTRB practice inherited from MIL-STD-750-1 puts the junction at Tj,max — 150–175 °C for SiC — with drain-source bias at 80% of rated blocking voltage for 1000 h. None of this was written for silicon carbide, which is precisely why JC-70.2 exists, and why the JEP documents adjust how these stresses are applied and read rather than replacing the need for them.

The consequence for the test floor is the reason this article exists. A SiC qualification plan is assembled from guidelines rather than run from one named sequence, so the ATE has to hold arbitrary bias and temperature combinations for the full stress duration instead of executing a fixed script — with per-device fail isolation and interim parametric reads at 168, 500 and 1000 h, because a lot is 3 lots × 77 units and one shorted die must not collapse bias on the rest.