Intepro Systems

HTRB Testing Explained: Bias, Temperature, Leakage and What the Rig Has to Guarantee

Power semiconductors · 3 min read · 11 cited facts

High-temperature reverse bias is conceptually the simplest reliability test there is. Hold a device at its maximum junction temperature, apply reverse bias across the blocking junction, wait a thousand hours, and see whether the leakage current went anywhere it should not have. There is no waveform to synthesise and nothing to sequence.

Which is exactly why the rig is harder than it looks. When the test is a single condition held for six weeks, everything that matters is about holding it precisely and not losing the lot.

The conditions

ParameterValueClause
HTRBTj = Tj,max (150–175 °C for SiC), V_DS = 80% of rated blocking voltage, 1000 hMIL-STD-750-1 M1038/M1039 + JEDEC practice
HTOLTj ≥125 °C, Vcc ≥ Vcc,max, 3 lots × 77 units, 1000 h, 0 failsJESD47
H3TRB / THB85 °C / 85% RH, reverse bias 80% of rated V capped at 100 V, 1000 hJESD22-A101 / AEC-Q101
HTRB and related stress conditions

Note the 100 V cap on H3TRB. It exists because self-heating at higher bias dries the package and defeats the humidity the test depends on. High-voltage variants remove that cap and add continuous leakage monitoring, which is a materially different rig — worth confirming which one your qualification plan actually calls for.

Bias accuracy is the acceleration variable

The whole inference of a reliability test is that stress applied now predicts failures later. That inference runs through the applied bias. Error in the bias is error in the acceleration factor, which is error in the lifetime you report. Everything else in the rig is negotiable; this is not.

Channel count decides your calendar

JESD47 asks for three lots of 77 units. That is 231 devices under bias, and the number of channels you can run in parallel sets how long a qualification takes rather than how much power you need. Programmes routinely specify a rig on voltage and current, then discover the schedule was set by channel density all along.

Interim reads are the difference between data and an autopsy

Parametric measurements at 168, 500 and 1000 hours turn a pass/fail into a trend. Without them you learn that a device failed; with them you can often see it drifting first, which is the information that changes a design rather than merely rejecting a lot. Building interim reads into the sequence is far easier than retrofitting them.

Specifying a reliability rig?

Tell us device class, blocking voltage, lot size and channel count. We will come back with an architecture and be clear about where the schedule constraint actually sits.

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